搜索资源列表
BPSK
- 在quartus ii下完成的用VHDL语言编写的数字式调频BPSK的调制，其中DDS和成型滤波使用ip核完成-Accomplished in quartus ii the use of VHDL language digital FM BPSK modulation, which use the ip filter DDS and forming complete nuclear
sixiangzaibosheji
- 本代码采用Altera公司的FPGA为主控芯片，以开发软件QuartusⅡ为工具。采用EDA设计中的自顶向下与层次式设计方法使用精简的DDS算法完成了输入为14MHz，输出四路频率为70MHz的四相序正弦载波（相位分别为0°、90°、180°、270°）的设计。利用Verilog HDL语言进行了程序设计并用QuartusⅡ对设计进行了仿真，验证了其正确性。-DDS algorithm with simplified input for the completion of 14MHz, 70M
Signal-Generator-VHDL
- 这是基于quartus dds信号发生器设计的源程序-This is based on quartus dds source signal generator design
MIF_file_of_Sine_Wave_Generator
- 在Quartus的DDS设计中，通常会用到mif或者hex文件存储函数值，被ROM的IP模块调用。本程序是在Matlab环境下，根据所需数据位数和长度自定义mif文件。-Quartus DDS design, usually used in the mif or hex file storage function value, call the ROM of IP modules. This program is in the Matlab environment, according to t
DDS_FPGA
- 一个DDS信号发生器的设计 Quartus 下实现
ADDA_restored
- 一个AD采样，DDS产生的简易测试程序 HDL语言 Quartus测试程序
8bitDDS
- 在QUARTUS II 8.0下做的基于DDS的多功能调制器，可实现ASK、FSK、BPSK调制。用SIGNALTAP仿真测试正确。-A In multi-function modulator based on DDS in QUARTUS II 8.0 , can realize the ASK, FSK, BPSK modulation. With SIGNALTAP simulation test right.
sopc_lcd_led
- 利用De0_nano建立的SOPC系统，其中包含有LCD，LED，DDS函数发生和ADC等源程序。工程编译环境为Quartus II 11.0，eclipse for sopc。-Established by De0_nano SOPC system, which includes LCD, LED, DDS functions occurrence and ADC and other source. Project build environment for the Quartus II 11
9
- dds xinhaofashengqi quartus vhdl
DDS_total
- quartus下的DDS信号源设计，可实现多种波形不同频率和幅度的切换，人机界面友好。-design the quartus under the DDS source, can achieve a variety of waveforms of different frequencies and amplitude switching, friendly interface.
ep1c12_29_dds
- DDS设计：该程序完成了在Quartus Ⅱ上使用VHDL语言实现的DDS波形调制设计-DDS Design: The procedure is completed in Quartus ii the DDS waveform modulation design using VHDL language
DDS_shiyan
- 用quartus编程实现的直接数字频率合成器（DDS）-The quartus programming direct digital frequency synthesizer (DDS)
dds_work
- verilog语言编写，在Quartus II里仿真DDS的产生，包括所有仿真生成的相关文件--verilog language in the Quartus II DDS in the generation of simulation, including all documents generated by the simulation,
DDSpro
- DDS技术的设计代码，利用quartus II编写，供大家参考-DDS technology design code
11071221593477
- 关于quartus ii设计的dds源代码-About quartus ii design dds source code
DDSN
- quartus II 13.0 DDS工程文件，采用VHDL编写，可输出正交两路正弦信号。可以直接用modelsim-alter 仿真-quartus II 13.0 DDS project file, using VHDL written two orthogonal sinusoidal output signals. Can be simulated directly modelsim-alter
DDDDDDDDDSSS
- FPGA实现DDS正弦波、方波、三角波发生器Verilog程序（已验证）Quartus工程文件-FPGA realization DDS sine, square, triangle wave generator Verilog program (verified) Quartus Project Files
vftvdr
- 基于FPGA的DDS信号发生器设计，包含Quartus 的工程，打开即可使用，Verilog 语言编写！-The DDS signal generator based on FPGA design, including the Quartus project, open to use, Verilog language! 朗读 显示对应的拉丁字符的拼音 字典- 查看字典详细内容-FPGA design, including the Quartus project, open to use, Ve